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NB4L339 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer
Multi-Level Inputs w/ Internal Termination
Description
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1
The NB4L339 is a multi-function Clock generator featuring a 2:1 Clock multiplexer front end and simultaneously outputs a selection of four different divide ratios from its four divider blocks; /1//2//4//8. One divide block has a choice of /1 or / 2. The output of each divider block is fanned-out to two identical differential LVPECL copies of the selected clock. All outputs provide standard LVPECL voltage levels when externally terminated with a 50-ohm resistor to VCC - 2 V. The differential Clock inputs incorporate internal 50-W termination resistors and will accept LVPECL, CML or LVDS logic levels. The common Output Enable pin (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced to the negative edge of the clock input. This device is housed in a 5x5 mm 32 pin QFN package.
Features
1
32
QFN32 MN SUFFIX CASE 488AM
NB4L339 AWLYYWWG G
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
* * * * * * * * * * * * * * * *
Maximum Input/Output Clock Frequency > 700 MHz Low Skew LVPECL Outputs, 15 ps typical 1 ns Typical Propagation Delay 150 ps Typical Rise and Fall Times 0.15 ps Typical RMS Phase Jitter 0.5 ps Typical RMS Random Clock Period Jitter LVPECL, CML or LVDS Input Compatible Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V LVPECL Output Level; 750 mV Peak-to-Peak, Typical Internal 50-W Input Termination Provided Synchronous Output Enable/Disable Asynchronous Master Reset Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices -40C to 85C Ambient Operating Temperature 32-Pin QFN, 5 mm x 5 mm This is a Pb-Free Device
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
January, 2007 - Rev. P2
Publication Order Number: NB4L339/D
NB4L339
DIVSEL A /1 / /2 R B /2 R A QA0 QA0 foutA = 622.08 MHz QA1 or 311.04 MHz QA1 QB0 QB0 QB1 QB1
CLKSEL
CLKA VTA CLKA CLKB VTB CLKB EN
50-W 50-W
B
foutB = 311.04 MHz
EXAMPLE: fin = 622.08 MHz 50-W 50-W EN C /4 R C QC0 QC0 foutC = 155.52 MHz QC1 QC1 QD0 QD0 QD1 QD1
D /8 R
D
foutD = 77.76 MHz
MR
Figure 2. Detailed Logic Diagram Table 1. Input Select Function Table
CLKSEL* 0 1 CLK Input Selected CLKA CLKB
Table 2. Divider Select Function Table
DIVSEL* 0 1 QA Divide Divide by 1 Divide by 2
Table 3. Clock Enable/Disable Function Table
CLK Input Low to High Transition High to Low Transition X (Don't Care) * Pin will default LOW when left OPEN. EN* 0 1 X (Don't Care) MR** H H L Function Divide - Outputs Active Hold Q - Outputs Inactive Reset Q
** Pin will default HIGH when left OPEN. DIVSEL
QA0
QA0
QA1
QA1
VCC
VEE CLKA VTA CLKA CLKB VTB CLKB VEE
32 31 1 2 3 4 5 6 7 8 9 10
30 29 28 27
26 25 24 Exposed Pad (EP) 23 22 NB4L339 21 20 19 18
VCC
MR
QB0 QB0 QB1 QB1 QC0 QC0 QC1 QC1
11
12 13 14
17 15 16
VCC
QD1
QD1
QD0
QD0
Figure 3. Pinout QFN-32 (Top View) http://onsemi.com
2
CLKSEL
VCC
EN
NB4L339
Table 4. Pin Description
Pin 1, 8, EP 2 3 4 5 6 7 9, 16, 25, 32 10 11 12 13 14 15 17 18 19 20 21 22 23 24 26 27 28 29 30 31 - Name VEE CLKA VTA CLKA CLKB VTB CLKB VCC CLKSEL QD1 QD1 QD0 QD0 EN QC1 QC1 QC0 QC0 QB1 QB1 QB0 QB0 MR QA1 QA1 QA0 QA0 DIVSEL EP I/O - LVPECL, CML, LVDS Input - LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input - LVPECL, CML, LVDS Input - LVCMOS/LVTTL LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVCMOS/LVTTL LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVCMOS/LVTTL LVPECL Output LVPECL Output LVPECL Output LVPECL Output LVCMOS/LVTTL - Negative Supply Voltage Non-inverted differential input (A). (Note 1) Internal 100-W center-tapped termination pin for CLKA and CLKA (Note 1). Inverted differential input (A). (Note 1) Non-inverted differential input (B). (Note 1) Internal 100-W center-tapped termination pin for CLKB and CLKB. (Note 1) Inverted differential input (B). (Note 1) Positive Supply Voltage Asynchronous Clock input select pin. This pin defaults LOW when left open with 80 kW resistor to VEE. Inverted differential (D1) output. Typically terminated with 50 W resistor to VCC - 2 V Non-inverted Differential (D1) Output. Typically terminated with 50 W resistor to VCC - 2 V. Inverted differential (D0) output. Typically terminated with 50 W resistor to VCC - 2 V. Non-inverted Differential (D0) Output. Typically terminated with 50 W resistor to VCC - 2 V. Synchronous Output Enable/Disable pin. This pin defaults LOW when left open with 80 kW resistor to VEE. Inverted differential (C1) output. Typically terminated with 50 W resistor to VCC - 2 V. Non-inverted Differential (C1) Output. Typically terminated with 50 W resistor to VCC - 2 V. Inverted differential (C0) output. Typically terminated with 50 W resistor to VCC - 2 V. Non-inverted Differential (C0) Output. Typically terminated with 50 W resistor to VCC - 2 V. Inverted differential (B1) output. Typically terminated with 50 W resistor to VCC - 2 V. Non-inverted Differential (B1) Output. Typically terminated with 50 W resistor to VCC - 2 V. Inverted differential (B0) output. Typically terminated with 50 W resistor to VCC - 2 V. Non-inverted Differential (B0) Output. Typically terminated with 50 W resistor to VCC - 2 V. Master Reset Asynchronous. This pin defaults HIGH when left open with 80 kW resistor to VCC. Inverted differential (A1) output. Typically terminated with 50 W resistor to VCC - 2 V. Non-inverted Differential (A1) Output. Typically terminated with 50 W resistor to VCC - 2 V. Inverted differential (A0) output. Typically terminated with 50 W resistor to VCC - 2 V. Non-inverted Differential (A0) Output. Typically terminated with 50 W resistor to VCC - 2 V. Asynchronous Divide Select Pin selects A divide block outputs to divide by 1 or divide by 2. Defaults LOW when left open, divide-by-1, with 80 kW resistor to VEE. Exposed Pad. The exposed pad (EP) on package bottom (see case drawing) is thermally connected to the die for improved heat transfer out of package and must be attached to a heat-sinking conduit. The pad is electrically connected to VEE and must be connected to VEE on the PC board. Description
1. In the differential configuration when the input termination pin (VTx / VTx) are connected to a common termination voltage or left open, and if no signal is applied on CLKx / CLKx input then the device will be susceptible to self-oscillation.
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NB4L339
Table 5. ATTRIBUTES
Characteristics Input Default State Resistors ESD Protection Moisture Sensitivity (Note 2) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Human Body Model Machine Model QFN-32 Oxygen Index: 28 to 34 Value 80 kW > 2.0 kV > 100 V Level 1 UL 94 V-0 @ 0.125 in 366
Table 6. MAXIMUM RATINGS
Symbol VCC VIO VINPP IIN IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input/Output Voltage Differential Input Voltage Swing |CLK - CLK| Static Surge Continuous Surge QFN-32 Condition 1 VEE = 0 V VEE = 0 V -0.5 = VIo VCC + 0.5 Condition 2 Rating 4.0 4.0 2.8 45 80 50 100 -40 to +85 -65 to +150 0 LFPM 500 LFPM (Note 3) QFN-32 QFN-32 QFN-32 31 27 12 265 Units V V V mA mA C C C/W C/W C
Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder (Pb-Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4L339
Table 7. DC CHARACTERISTICS, CLOCK Inputs, LVPECL Outputs
VCC = 2.375 V to 3.6 V, VEE = 0 V, TA = -40C to +85C (Note 5) Symbol IEE VOH Characteristic Power Supply Current (Inputs and Outputs Open) Min 58 Typ 70 Max 90 Unit mA
LVPECL Outputs (Note 4) Output HIGH Voltage VCC = 3.3 V VCC = 2.5 V VOL Output LOW Voltage VCC = 3.3 V VCC = 2.5 V Differential Input Driven Single-Ended (see Figures 6 & 8) Vth VIH VIL VISE VIHD VILD VCMR VID IIH IIL VIH VIL IIH IIL Input Threshold Reference Voltage Range (Note 6) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Single-ended Input Voltage (VIH - VIL) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) (Note 8) Differential Input Voltage Swing (VIHD - VILD) Input HIGH Current Input LOW Current CLKx / CLKx CLKx / CLKx (VTx Open) (VTx Open) 1125 Vth + 75 VEE 150 VCC - 75 VCC Vth - 75 2800 mV mV mV mV VCC - 1135 2155 1355 VCC - 1935 1355 555 VCC - 1020 2280 1480 VCC - 1770 1530 730 VCC - 760 2540 1740 VCC - 1560 1740 940 mV
mV
Differential Inputs Driven Differentially (see Figures 7 & 9) 1200 VEE 1125 150 10 -10 VCC VCC - 150 VCC - 75 2800 40 10 mV mV mV mV mA mA
Single-Ended LVCMOS / LVTTL Control Inputs Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Input HIGH Current Input LOW Current CLKSEL, DIVSEL, EN MR CLKSEL, DIVSEL, EN MR 2000 VEE 40 -10 -10 -115 VCC 800 115 10 10 -40 mV mV mA mA
Termination Resistors RTIN RTIN Internal Input Termination Resistor (Measured across CLKx and CLKx) Internal Input Termination Resistor (Measured from CLKx to VTx) 80 40 100 50 120 60 W W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs require 50 W receiver termination resistors to VCC - 2 V for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth is applied to the complementary input when operating in single-ended mode. 7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 8. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
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NB4L339
Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, VEE = 0 V (Note 9)
-40_C Symbol finmax VOUTPP tPLH, tPHL trr DCO tSKEW ts th tPW FN Characteristic Maximum Input CLOCK Frequency Output Voltage Amplitude (@ VINPPmin) (See Figure 4) fin 622 MHz Propagation Delay to Output Differential / 1 Reset Recovery Output CLOCK Duty Cycle Within Device Skew (Note 11) Device to Device Skew (Note 12) Setup Time @ 50 MHz Hold Time @ 50 MHz Minimum Pulse Width Phase Noise EN to CLKx DIVSEL to CLKx CLKx to EN CLKx to DIVSEL MR fin = 622.08 MHz Outputs (A) Div by 1 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz tJIT1 Integrated Phase Jitter (Figure 4) fin = 622.08 MHz, 12 kHz - 20 MHz Offset All Divides Random Clock Period Jitter (Note 13) fin = 622.08 MHz VINPP tr, tf NOTE: Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14) Output Rise/Fall Times @ 622.08 MHz input frequency (20% - 80%) All Divides 150 150 250 0.5 1.5 150 150 250 0.5 1.5 150 150 250 0.5 1.5 -136 -136 -141 -141 -141 -141 ps RMS ps RMS mV ps 900 -100 800 0 5.0 All Divides CLKx/CLKx to Qx/Qx MR to Qx CLKSEL to Qx Min 700 530 0.8 1.2 0.8 4.0 40 30 90 60 60 190 900 -100 800 0 5.0 730 1.0 - 1.0 1.3 5.0 1.3 Typ Max Min 700 530 0.8 1.2 0.8 4.0 40 30 90 60 60 190 900 -100 800 0 5.0 ns dBc ps 730 1.0 - 1.0 1.3 5.0 1.3 25_C Typ Max Min 700 530 0.8 1.2 0.8 4.0 40 30 90 60 60 190 730 1.0 - 1.0 1.3 5.0 1.3 85_C Typ Max Unit MHz mV ns
ns % ps ps
0.15
0.25
0.15
0.25
0.15
0.25
tJIT2
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPP (Min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC - 2 V Input edge rates 100 ps (20% - 80%). 10. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 50 MHz. 11. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross-point of the inputs to the cross-point of the outputs. 12. Device to device skew is measured between outputs under identical transition @ 50 MHz. 13. Additive RMS jitter with 50% duty cycle clock signal; all inputs and outputs active. 14. VINPP (Max) cannot exceed VCC - VEE. Input voltage swing is a single-ended measurement operating in differential mode.
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NB4L339
Figure 4. NB4L339 vs. Agilent 8665A 622.08 MHz at 3.3 V, Room Ambient
VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) 800 700 600 500 400 300 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) at Ambient Temperature (Typical) Application Information
The NB4L339 is a high-speed, Clock multiplexer, divider and low skew fan-out buffer featuring a 2:1 Clock multiplexer front end and outputs a selection of four different divide ratios; /1/2/4/8. One divide block has a choice of /1 or / 2. The outputs of all four divider blocks are fanned-out to two pair of identical differential LVPECL copies of the selected clock. All outputs provide standard LVPECL voltage levels when externally terminated with a 50-ohm resistor to VTT = VCC - 2 V. The differential Clock input buffers incorporate internal 50-W termination resistors in a 100-W center-tapped configuration and are accessible via a VTx pin. This feature provides transmission line termination on-chip, at the receiver end, eliminating external components. Inputs CLKA/B and CLKA/B must be signal driven or auto oscillation may result.
The NB4L339 Clock inputs can be driven by a variety of differential signal level technologies including LVDS, LVPECL, or CML. The internal dividers are synchronous to each other. Therefore, the common output edges are precisely aligned. The Output Enable pin (EN) is synchronous so that the internal divider flip-flops will only be enabled/disabled when the internal clock is in the LOW state. This avoids any chance of generating a runt pulse on the internal clock when the device is enabled/disabled, as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced to the negative edge of the clock input. The Master Reset (MR) is asynchronous. When MR is forced LOW, all Q outputs go to logic LOW.
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NB4L339
MR
CLK Q (/1) Q (/2) Q (/4) Q (/8)
Figure 6. Timing Diagram
CLK MR tRR tRR
Q (/n) NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK, following a high-to-low clock transition.
Figure 7. Master Reset Timing Diagram
Internal Clock Disabled CLK Q (/n) EN
Internal Clock Enabled
Figure 8. Output Enable Timing Diagrams
The EN signal will "freeze" the internal divider flip-flops on the first falling edge of CLK after its assertion. The internal divider flip-flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next
falling edge of CLK, then the internal divider flip-flops will "unfreeze" and continue to their next state count with proper phase relationships.
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NB4L339
CLK CLKn 50 W VTn 50 W CLKn Vth Vth
CLK
Figure 10. Differential Input Driven Single-Ended
Figure 9. Input Structure
CLK VCC Vthmax
VIHmax VILmax CLK VIH Vth VIL VIHmin VILmin VCC VCMmax CLK VCMR CLK
CLK
Figure 12. Differential Inputs Driven Differentially
Vth
Vthmin VEE
Figure 11. Vth Diagram
VIHDmax VILDmax VIHDtyp VILDtyp VIHDmin VILDmin
VID = VIHD - VILD
CLK CLK
VID = |VIHD(CLK) - VILD(CLK)| VIHD VILD
VCMmax
VEE
Figure 13. Differential Inputs Driven Differentially
Figure 14. VCMR Diagram
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH NOTE: VEE VIN VCC; VIH > VIL
Figure 15. AC Reference Measurement
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NB4L339
VCC VCC VCC VCC
Zo = 50 W LVPECL Driver VT = VCC - 2.0 V
NB4L339 CLKx 50 W 50 W LVDS Driver
Zo = 50 W VT = OPEN
NB4L339 CLKx 50 W 50 W
Zo = 50 W CLKx GND
CLKx
Zo = 50 W CLKx
CLKx
GND
GND
GND
Figure 16. LVPECL Interface
Figure 17. LVDS Interface
VCC
VCC
Zo = 50 W CML Driver VT = VCC
NB4L339 CLKx 50 W 50 W
Zo = 50 W
CLKx
GND
GND
Figure 18. Standard 50 W Load CML Interface
VCC
VCC
VCC
VCC
Zo = 50 W Differential Driver VT = VREFAC*
NB4L339 CLKx 50 W 50 W Single-Ended Driver
Zo = 50 W VT = VREFAC*
NB4L339 CLKx 50 W 50 W CLKx (open)
Zo = 50 W
CLKx
GND
GND
GND
GND
Figure 19. Capacitor-Coupled Differential Interface (VT Connected to External VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor.
Figure 20. Capacitor-Coupled Single-Ended Interface (VT Connected to External VREFAC)
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NB4L339
ZO = 50 W Q Driver Device ZO = 50 W Q 50 W 50 W D D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 21. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices)
ORDERING INFORMATION
Device NB4L339MNG NB4L339MNR2G Package QFN-32 (Pb-free) QFN-32 (Pb-free) Shipping 74 Units / Tray 1000 / Tape & Reel
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB4L339
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D
A B
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
32 X b 0.10 C A B
0.05 C BOTTOM VIEW 0.28
32 X 28 X
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
TOP VIEW SIDE VIEW
9 8
PIN ONE LOCATION
E
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
5.30 3.20
D2
K
17 32 X
E2
1 32 25 24
0.63
32 X
e
3.20
5.30
0.50 PITCH
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB4L339/D

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